Method of parallelization of loops for grid calculation problems on GPU accelerators

А.Yu. Doroshenko, O.G. Beketov


The formal parallelizing transformation of a nest of calculation loop for SIMD architecture devices, particularly for graphics processing units applying CUDA technology and heterogeneous clusters is developed. Procedure of transition from sequential to parallel algorithm is described and illustrated. Serialization of data is applied to optimize processing of large volumes of data. The advantage of the suggested method is its applicability for transformation of data which volumes exceed the memory of operating device. The experiment is conducted to demonstrate feasibility of the proposed approach. Technique presented in the provides the basis for further practical implementation of the automated system for parallelizing of nested loops.

Problems in programming 2017; 1: 59-66


automatic parallelization; loop optimization; general-purpose computing on graphics processing units


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